Sidebar 2: Varèse Unwrapped
The Varèse Core, pictured above—photo by Paul Miller—is the largest component in the system. All calls between boxes are integrated here, and the Core generates the system clock if the external Varèse Master Clock is not connected.
As the system hub, the Core is home to all the upsampling, the primary digital filtering, and a good deal of the modulation—truncation and the noise-shaping—but not the bit mapping, which happens on a dynamic basis within the Mono Ring DACs. More about this later.
All data, clock, and other signals are sent among the five Varèse boxes (six with the transport) via the proprietary ACTUS link. dCS's Tomix clock system employs two crystal oscillators in the Master Clock, one of them (for 88.2kHz) oven controlled (OCXO), the other (slaved to the first for 96kHz) voltage-controlled (VXCO). The onboard FPGA calculates an absolute time stamp and embeds it in the inter-box data, ensuring exact time-alignment between the L and R channels without increasing data-related jitter.
Ringing in the changes: The Mono DAC's summing, gain, and output stages are based on those in the Vivaldi APEX. The summing and primary filtering stage is op-amp based, a cascade of Linear Technology and National ICs. It's here that the 0.2V, 0.6V, 2V, and 6V gain options are set. Some final analog filtering acts above 150kHz to ensure that any residual stopband artefacts are gently polished off.
Before all this comes the Ring DAC itself, and although the resistor matrix and latches are unchanged in the Varèse, both are now arranged as 2×48 current source rings—a pair of Ring DACs within each Mono DAC running in differential mode with all the potential for reduced noise, even-order distortion, etc. that that implies. For the APEX update, dCS paid particular attention to the latches that address the matrix, tightening up the clocking and reducing the source impedance of the reference PSU, achieving a measurable reduction in low-level phase noise. However, the current drawn from the reference supply was still signal dependent—a possible source of correlated ripple—which is avoided by the Varèse's differential mode, ensuring that the current flow is now signal independent. More attention is also paid to the very high-frequency matrix switching noise; this is particularly important with the M1 and M3 mapping options, which run at twice the rate of the legacy M2 mapper.
Decoding the matrix: To understand why the mapping of data to the matrix is key to the Varèse's sound, we need to remind ourselves how the Ring DAC works. The Varèse Core upsamples then decimates incoming LPCM data (and converts DSD) to an average word length of 4.6 bits. These 24 (24.6) possible values are then mapped across the 48 notionally identical current sources that comprise the Ring DAC. This matrix of resistor elements is visible in the Mono DAC's lid-off shot (see the ">David Steven interview) along with the fully balanced, APEX-derived analog output stages.
For the Ring DAC to be truly monotonic (like a pure 1-bit DSD DAC) these 48 current sources would need to be absolutely identical, which they are not. So dCS "randomizes" the mapping of bits to these elements. Fixed digital errors, which would be realized as harmonic distortion, are thus traded for an inaudible increase in noise. In practice, this sample-by-sample selection across the matrix is not truly random but is based on the historical and current data flow.—Paul Miller
The Varèse Core, pictured above—photo by Paul Miller—is the largest component in the system. All calls between boxes are integrated here, and the Core generates the system clock if the external Varèse Master Clock is not connected.
As the system hub, the Core is home to all the upsampling, the primary digital filtering, and a good deal of the modulation—truncation and the noise-shaping—but not the bit mapping, which happens on a dynamic basis within the Mono Ring DACs. More about this later.
All data, clock, and other signals are sent among the five Varèse boxes (six with the transport) via the proprietary ACTUS link. dCS's Tomix clock system employs two crystal oscillators in the Master Clock, one of them (for 88.2kHz) oven controlled (OCXO), the other (slaved to the first for 96kHz) voltage-controlled (VXCO). The onboard FPGA calculates an absolute time stamp and embeds it in the inter-box data, ensuring exact time-alignment between the L and R channels without increasing data-related jitter.
