Wadia Digimaster X-32 digital processor Page 2
Most of the X-32's digital electronics have been condensed into two large programmable gate arrays. These chips allow the designer to configure the chip's logic gates in any arrangement, producing custom monolithic devices for a fraction of the cost of developing a dedicated custom IC. The X-32 uses one 64-pin and one 84-pin gate array. Together, they replace about 35 conventional ICs. In addition to reducing the parts count (thereby reducing cost, size, and power consumption while increasing reliability) and the amount of RF energy radiated from the circuit board traces, programmable gate arrays can be restructured by reprogramming the ROM chip that determines its configuration. The gate arrays can be made into any type of logic circuits the designer wishes just by changing the ROM instructions. As we shall see, this flexibility is particularly useful and was needed sooner than Wadia had anticipated.
A major problem with outboard decoders is the fact that the decoder's timing reference is embedded in the S/PDIF digital output from the digital source. A single line from a CD transport or DAT machine carries left and right audio-channel data as well as the clock. This interface format is particularly prone to jitter, a time-axis variation in the signal. There is a host of variables that introduce jitter into the S/PDIF signal an outboard digital decoder sees. These variables include the CD player's intrinsic jitter, its output driver characteristics, cable characteristics, receiving-circuit input characteristics, and the relationship between them (footnote 1) Jitter in the clock signal is particularly deleterious since the decoder's timing reference is a constantly shifting signal. The result is reduced soundstage depth, hardness, and glare, along with a lack of ease and musicality. Ideally, the outboard processor would send a clock signal to the CD transport, which is slaved to the processor (footnote 2). In the professional PCM-1630 format used to make virtually all CD master tapes, the 1630 processor sends a video sync signal to the ¾" U-Matic video recorder that servos the capstan speed, thus locking the VTR's data transmission to the digital processor. Unfortunately, the standard for consumer digital audio transmission is the single unbalanced RCA cable, with no provision for synchronizing the data source (footnote 3).
Wadia has addressed this problem with a circuit called the "Rock Lok" that reclocks the incoming data from a CD player or DAT machine. The Rock Lok is said to reduce recovered clock jitter by a factor of 2500 over standard Phase Lock Loop (PLL) circuits. Instead of using a PLL to synchronize the processor with the incoming data, the Rock Lok generates an entirely new clock from a crystal oscillator based on the average clock frequency of the incoming data stream. The average input frequency is calculated and the quartz oscillator is matched to this frequency by pulling its clock speed slightly. All clocking within the X-32 is based on this quartz-crystal standard instead of a clock extracted from the S/PDIF input. A quarter of one of the gate arrays forms the Rock Lok circuit.
There have, however, been some problems in the field because of this circuit. Many people bought X-32s only to discover that they would not lock to their CD players' digital outputs. According to Wadia, the problem lies in CD players that do not meet the EIAJ specification for clock frequency accuracy and clock jitter. To be classified as "Level 1: High Accuracy," the source clock's jitter must be less than 20 nanoseconds (20ns or 0.00000002s), measured at the half-voltage points. If the CD player or DAT machine's digital output doesn't meet this criterion (with an additional tolerance of ±50%), the X-32 will reject the signal. Wadia has solved this problem by supplying with each X-32 an additional Read-Only Memory (ROM) chip. The socket-mounted ROM that comes in the unit configures the programmable gate-array chips described earlier. If the X-32 will not lock to your CD player, the ROM must be replaced with the extra chip supplied, which fortunately is very simple to do. The X-32 will now accept a wider range of digital inputs, but at the expense of less clock-jitter reduction: The 2500:1 jitter reduction with the stock chip becomes 10:1 with the optional ROM. This ability to adapt the processor easily to new or unexpected conditions exemplifies the flexibility of programmable gate arrays. With digital converter technology changing so rapidly, and in light of the immediate need to adapt to various transports, the decision to use gate arrays rather than fixed chips appears prudent.
It is commendable of Wadia to build their decoders to the highest performance criteria by shipping the X-32 with the Level One ROM. However, I do have some reservations about asking consumers to replace chips, especially when inserting the new chip backwards in the socket could result in damage to the main printed circuit board. It is advisable to ask your dealer to perform this operation (footnote 4).
Oversampling is performed by two AT&T Digital Signal Processing (DSP) chips which, together, have the computing power of 50 IBM PCs or 36MIPS (Million Instructions Per Second). These powerful chips compute the interpolated points between samples, which occur every 44,100ths of a second from a CD. The controlling DigiMaster software, which includes the FrenchCurve time-domain filtering, is found on four (two for each DSP chip) ROMs.
The final technical aspect of the X-32 I'll discuss is also its most interestingand controversial: digital-to-analog conversion. There has been some discussion over Wadia's claim of 64x oversampling in the 2000 Digital Decoding Computer. Since the X-32 uses the same technique as the 2000 to achieve high oversampling rates, this is an appropriate time to discuss how the X-32and, by extension, the 2000work. Rather than take sides in the debate, I will merely describe the X-32 in technical terms and let the readers draw their own conclusions.
Wadia's critics maintain that the claimed high oversampling rates (64x in the 2000, 32x in the X-32) are misleading since they are not achieved exclusively in the digital domain. In the X-32, the two AT&T DSP chips working in parallel perform 8x oversampling. This 8x-oversampled signal is input to shift registers that temporarily store data as they are clocked through. A shift register can be thought of as a "bucket brigade": data come in one end and move one step toward the output with each clock cycle. Taps positioned at intermediate points along the bucket brigade access the same data, but at slightly shifted times. The shift registers, in addition to acting as delay lines, clock data to the DACs.
Footnote 1: See Peter Van Willenswaard's "Industry Update" in Vol.13 No.5 for a description of these factors as well as a do-it-yourself circuit for optimizing data transmission from CD player to decoder.
Footnote 2: Sony's expensive two-box processor from 1988, the R1, did have a separate optical clock connection from the transport to the processor.
Footnote 3: When I visited JVC's laboratory in Japan last year, I saw an outboard digital processor and transport that had a separate cable for sending a clock back to the transport. JVC has no plans to market the processor in this country.
Footnote 4: See Wadia's Technical Bulletin No.5, Rev 3/22/90, for a description of this problem and how to install the new ROM.